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-- Company: 
-- Engineer: 
-- 
-- Create Date:    19:43:19 02/04/2010 
-- Design Name: 
-- Module Name:    PassThrough - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity PassThrough is
	Port( IMG_I2C_Clk : out std_logic;
			IMG_I2C_Data : out std_logic;
			IMG_Data : in std_logic_vector(9 downto 0);
			IMG_PIXEL_Clk : in std_logic;
			IMG_ROW_Clk : in std_logic;
			IMG_ROW_EN : in std_logic;
			IMG_VSYNC : in std_logic;
			IMG_RST : out std_logic;
			
			OEM_I2C_Clk : out std_logic;
			OEM_I2C_Data : out std_logic;
			OEM_Data : out std_logic_vector(9 downto 0);
			OEM_PIXEL_Clk : out std_logic;
			OEM_ROW_Clk : out std_logic;
			OEM_ROW_EN : out std_logic;
			OEM_VSYNC : out std_logic;
			
			SW : in std_logic_vector(3 downto 0);
			LED : out std_logic_vector(3 downto 0));
end PassThrough;

architecture Behavioral of PassThrough is

	signal data : std_logic_vector(9 downto 0);

begin

	IMG_RST<='1';
	
	OEM_I2C_Clk <= 'Z';
	IMG_I2C_Clk <= 'Z';
	OEM_I2C_Data <= 'Z';
	IMG_I2C_Data <='Z';
	OEM_Data <= data;
	OEM_PIXEL_Clk <= IMG_PIXEL_Clk;
	OEM_ROW_Clk <= IMG_ROW_Clk;
	OEM_ROW_EN <= IMG_ROW_EN;
	OEM_VSYNC <= IMG_VSYNC;
	
	LED<=SW;
	
	process(SW)
	begin
		if SW(3) = '0' then
			data<=IMG_Data;
		else
			data<=(others=>'1');
		end if;
	end process;
	
end Behavioral;

